1. Field of the Invention
The present invention relates to a process for etching hard materials, and particularly to a process for slope etching both ends of a hard material.
2. Description of the Prior Art
Such process for slope etching hard materials has been utilized in various technical fields, and recently applied to semiconductor devices, for the purpose of improving step coverage.
In order to form a desired pattern of a hard material layer in manufacturing semiconductor elements, photo processing and etching should be generally carried out. The etching is mainly classified into a dry etching process and a wet etching process, a suitable one of which is used depending on the existing conditions.
Recently, RIE (Reactive Ion Etching) method which is generally classified as the dry etching method is gradually and widely used in virtue of its convenience in processing, over the wet etching method using liquid chemicals.
The conventional process for forming a pattern of a hard material by utilizing the above-mentioned RIE method will now be described, in conjunction with FIGS. 1A to 1D.
First, a layer 2 for forming a predetermined pattern is deposited on a substrate 1, as shown in FIG. 1A. On the layer 2, a photoresist 3 is coated and then radiated with ultra violet under the condition that a photomask 4 provided with a predetermined pattern is aligned on the photoresist 3 to be in contact therewith. As a result, the photoresist 3 is partially removed, in order to form a photoresist pattern layer 3a having the predetermined pattern, as shown in FIG. 1B.
Thereafter, the pattern forming layer 2 for forming a desired pattern is subjected to an etch utilizing the RIE method which is an anisotropy dry etch method. After the photoresist pattern layer 3a is removed from the etched pattern forming layer 2, a pattern layer 2a having the corner angle of 90.degree. is formed, as shown in FIG. 1D.
However, this pattern forming process utilizing the conventional RIE method has a disadvantage that when a primary upper deposition layer 5 is coated on the pattern layer 2a etched according to the RIE method, the step coverage, that is the coverage of the deposition layer 5 over steps (the "K" portion in FIG. 2) formed at respective corners of about 90.degree. of the pattern layer 2a becomes poor, after the process integration. Consequently, the pattern layer 2a formed by the RIE method and a second upper deposition layer 6 formed on the primary upper deposition layer 5 are subject to a short failure, thereby causing the productivity of semi-conductor elements to be reduced.
Also, the process for forming a pattern of a hard material by utilizing the conventional wet etching method will now be described, in conjunction with FIGS. 3A to 3D.
First, a pattern forming layer 8 to be etched is deposited on a substrate 7, as shown in FIG. 3A. On the layer 8, a photoresist 9 is coated. Then, the photoresist 9 is exposed to ultra violet by using a photomask 10 printed with a predetermined pattern, and thereby developed to form a photoresist pattern layer 9a as shown in FIG. 3B. Thereafter, wet etching is carried out as shown in FIG. 3C. At this time, the pattern forming layer 8 is isotropically etched. This is because the velocity V.sub.S of the etching which proceeds on the interface between the photoresist 10 and the pattern forming layer 8 and in parallel to said interface is substantially identical to the velocity V.sub.D of the etching which proceeds in vertical to the surface of the element material. As a result, a pattern layer 8a is formed such that its lateral edges forms an angle of 45.degree. to the surface of substrate 7. As the photoresist pattern layer 9a is removed, the desired pattern layer 8a is formed, as shown in FIG. 3D.
However, this pattern forming process utilizing the conventional wet etching method also has a disadvantage that when a primary upper deposition layer 11 is coated on the pattern layer 8a etched according to the wet etching method, its step coverage over respective 45.degree. lateral edges of the pattern layer 8a becomes poor, as shown in FIG. 4. Consequently, the pattern layer 8a and a second upper deposition layer 12 formed on the primary upper deposition layer 11 are subject to a short failure at the portion "L" in FIG. 4. In particular, when the pattern layer 8a and the second upper deposition layer 12 form metal electrodes and the primary upper deposition layer forms an insulation layer, the pattern layer 8a and the second upper deposition layer 12 may be subject to a short or a break down at the portion "L", thereby causing the productivity of semi-conductor elements to be reduced.
Referring to FIG. 5, there is shown an example of conventional constructions of contact type image sensors. In the drawing, the reference numeral "13" designates a glass substrate, "14" a lower electrode, "14a" a gate electrode, "15", "15a" and "15b" insulation layers, that is Si.sub.x N.sub.y layers, "16" an amorphous silicon layer, "17" an upper electrode, "17a" a source electrode, "17b" a drain electrode, "18" an insulation layer, that is an ITO (indium thin oxide) layer, "19" a photodiode zone which is the zone receiving light corresponding to image, and "20" a thin film transistor (TFT) zone which is the zone transmitting signals.
In this case, the amorphous silicon layer 16 in the photodiode zone 19 has the thickness of about 8,000 .ANG. to about 1 .mu.m. The ITO layer 18 has the thickness of about 2,000 .ANG., while the lower electrode 14 has the thickness of about 2,000 .ANG.. Accordingly, the total thickness of the photodiode zone 19 is relatively as thick as about 1.2 .mu.m to about 1.4 .mu.m.
In the case of performing the RIE process by using a dry etching equipment, therefore, both sides of the photodiode zone 19, and particularly both sides of its amorphous silicon layer 16 form sharp vertical surfaces being at an angle of about 90.degree. to a horizontal plane. Since the amorphous silicon layer 16 has at its both sides sharp vertical surfaces, the ITO layer 18 and the upper electrode 17 coated on the amorphous silicon layer 16 has a thinner thickness at the zones m and n corresponding to the corner edges of the amorphous silicon layer 16, as compared to other zones. As a result, the step coverage of the ITO layer 18 and the upper electrode 17 over lateral edges of the amorphous silicon layer 16 becomes poor, thereby increasing the rate of poor products. Furthermore, the products tend to be weak against noise and damaged by a relatively low level of impact. Consequently, the overall performance of contact type image sensors is decreased.
In FIG. 5, the thin film transistor 20 which forms the signal transmitting zone comprises the glass substrate 13, the gate electrode 14a formed on the glass substrate 13, a low concentration amorphous silicon layer 16a and a high concentration amorphous silicon layer 16b which are formed as channel layers on the gate electrode 14a, and the source electrode 17a and the drain electrode 17b formed on the channel layers, respectively.
In similar to the photodiode zone 19, the low concentration amorphous silicon layer 16a and the high concentration amorphous silicon layer 16b functioning as channel layers have at their side edges step surfaces forming an angle of about 90.degree. to the horizontal plane, respectively, since they are anisotropically formed according to a dry etching method. As a result, the subsequently formed source and drain electrodes 17a and 17b have a step shape, so that the insulation layer 15a coated on the source and drain electrodes 17a and 17b has a thinner thickness at its both side edges than other areas. That is, the step coverage of the insulation layer 15a becomes poor, thereby causing the same problems as in the case of the photodiode zone 19.
When the gate electrode 14a of the thin film transistor 20 is anisotropically formed according to a dry etching method, it has at its side edges step surfaces forming an angle of about 90.degree. to the horizontal plane, as in the cases of the source and drain electrodes 17a and 17b and the photodiode zone 19. Accordingly, the step coverage of the subsequently coated layer on the gate electrode 14a becomes poor, so that the layer may be subject to a short failure, thereby causing the productivity of semi-conductor elements to be reduced.
In order to overcome the above-mentioned problems, various methods for slope etching a hard material layer have been proposed.
For example, a contact etching process of a method for manufacturing semi-conductor devices will now be described, in conjunction with FIGS. 6A to 6C.
First, an oxide layer 22 is formed on a substrate 21, as shown in FIG. 6A. Then, unnecessary part of the oxide layer 22 to be removed is defined by a photoresist 23 disposed on the oxide layer 22. The defined unnecessary part of oxide layer 22 is primarily wet etched by using a chemical solution, as shown in FIG. 6B. At this time, the photoresist 23 functions as a mask. Thereafter, the defined unnecessary part of oxide layer 22 is secondarily wet etched again, by using the photoresist 23 as a mask, as shown in FIG. 6C. According to this double etching, the oxide layer 22 has slant surfaces at its portions corresponding to respective opposite edges of formed contact. In this case, the slope angle of each edge of the contact can be adjusted by controlling the etch selectivity rate of the oxide layer 22 and the photoresist 23 upon wet or dry etching.
However, even when the etching is carried out under the condition of controlling the etch selectivity rate between the oxide layer 22 and the photoresist 23, it is difficult to smoothly slope each side surface of oxide layer 22 at a desired angle throughout the length thereof, because the slope of each corresponding surface of the photoresist 23 is vertical.
Otherwise, slope etching may be accomplished only by using the wet etching process, so far as the etch selectivity rate is properly controlled. In this case, however, the process is complex and requires expensive chemical etching solutions. Furthermore, the use of such chemical solutions results in increasing the possibility of the formation of glass layers at the boundary surfaces of the etched material.
Recently, the wet etching process has been commonly used, due to the above-mentioned problems.